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關(guān)于NAND flash的幾個(gè)縮寫(xiě)

SLC:Single-Level Cell

MLC:Multi-Level Cell

SB:Small Block=(512+16)Bytes/page

LB:Large Block=(2048+64)Bytes/page

DDP:Double Die Package

QDP:Quadruple Die Package

DSP:Double Stack Package

1P,2P,4P:Plane Plane 與CE無(wú)關(guān)

for example:SAMSUNG MLC---K9G4G08U0M為Normal MLC,K9L8G08U0M(DDP) is composed of two K9G4G08U0Ms,即DDP,有4Plane,1個(gè)CE,1個(gè)R/B,每個(gè)Plane由1024個(gè)Block和(2048+64)Byte page registers組成,一個(gè)Block有128個(gè)Page,每個(gè)Page有(2048+64)Byte,所以總容量為4*[1024*128*(2048+64)Byte+(2048+64)Byte]=8Gbit+256Mbit,MLC按page read & write(program),按block erase,Page寄存器大小與每個(gè)page的大小相同便于同步program.

  K9L8G08U0M雖然由2個(gè)K9G4G08U0M die封裝而成,但僅有一個(gè)CE和一個(gè)R/B,其控制chip #1 or #2讀寫(xiě)是由內部的R/B(#1),R/B(#2)信號來(lái)實(shí)現,Interleaving(交叉存取)過(guò)程中,Host通過(guò)發(fā)送F1h來(lái)詢(xún)問(wèn)chip #1的狀態(tài),發(fā)送F2h來(lái)詢(xún)問(wèn)chip #2的狀態(tài).

K9L8G08U0M(DDP) is composed of two K9G4G08U0Ms chips

K9HAG08U1M(QDP) is composed of two  K9L8G08U0M chips which are selected separately by each ~CE1 and ~CE2,R/B1 and R/B2

K9MBG08U5M (DSP) is composed of four  K9L8G08U0M chips which are selected separately by each ~CE1 ~CE2  ~CE3 ~CE4 ,R/B1 R/B2 R/B3 R/B4