下面一段話(huà)摘自S3C2440A數據手冊Nand Flash controller一章：
In recent times, NOR flash memory gets high in price while an SDRAM and a NAND flash memory is comparatively economical , motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM.
上面的話(huà)大意是由于Nor Flash價(jià)格比較貴，因而促使人們使用Nand Flash+SDRAM組合。
S3C2440A boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C2440A is equipped with an internal SRAM buffer called ‘Steppingstone’. When booting, the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed。
上面的話(huà)很好的概括了Nand controller的作用。
Generally, the boot code will copy NAND flash content to SDRAM. Using hardware ECC, the NAND flash data validity will be checked. Upon the completion of the copy, the main program will be executed on the SDRAM.
這段話(huà)就是講了怎樣使用Nand 啟動(dòng)的方法。
具體的操作方式見(jiàn)下圖：
上面的圖少了special function register控制流，具體的可以參考，S3C2410的。
During reset, Nand flash controller will get information about the connected NAND flash through Pin status (NCON(Adv flash), GPG13(Page size), GPG14(Address cycle), GPG15(Bus width) – refer to PIN CONFIGURATION), After power-on or system reset is occurred, the NAND Flash controller load automatically the 4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code in steppingstone is executed.
關(guān)于Steppgingstone手冊里的一句話(huà)是這么講的：
The NAND Flash controller uses Steppingstone as the buffer on booting and also you can use this area for another purpose
引腳配置（僅僅列出本開(kāi)發(fā)板配置情況）：
OM[1:0] = 00: Enable NAND flash memory boot
NCON: NAND flash memory selection(Normal / Advance)
0: Normal NAND flash(256Words/512Bytes page size, 3/4 address cycle)
GPG13: NAND flash memory page capacitance selection
1: Page=512Bytes(NCON = 0) or Page=2KBytes(NCON = 1)
GPG14: NAND flash memory address cycle selection
1: 4 address cycle(NCON = 0) or 5 address cycle(NCON = 1)
GPG15: NAND flash memory bus width selection
0: 8-bit bus width
My Nand flash configuration setting
Parts
Page size/Total size
NCON0
GPG13
GPG14
GPG15
K9F1208
512Byte/512Mbit
0
1
1
0
NAND FLASH MEMORY TIMING
TACLS和TWRPH0和TWRPH1這三個(gè)參數控制的是Nand Flash信號線(xiàn)CLE和ALE與寫(xiě)控制信號nWE的時(shí)序關(guān)系。
SOFTWARE MODE
S3C2440A supports only software mode access. Using this mode, you can completely access the NAND flash memory. The NAND Flash Controller supports direct access interface with the NAND flash memory。
下面是通過(guò)寄存器操作Nand Flash的方法，操作的寄存器和相應Nand Flash的對應關(guān)系：
Writing to the command register = the NAND Flash Memory command cycle
Writing to the address register = the NAND Flash Memory address cycle
Writing to the data register = write data to the NAND Flash Memory (write cycle)
Reading from the data register = read data from the NAND Flash Memory (read cycle)
Reading main ECC registers and Spare ECC registers = read data from the NAND Flash Memory
In the software mode, you have to check the RnB status input pin by using polling or interrupt.
Data Register Configuration
8-bit NAND Flash Memory Interface
Register
Endian
Bit [31:24]
Bit [23:16]
Bit [15:8]
Bit [7:0]
NFDATA
little
4th I/O[ 7:0]
3rd I/O[ 7:0]
2nd I/O[ 7:0]
1st I/O[ 7:0]
下面是Nand Flash的memory mapping圖，可以對照memory controller一章，可加深理解。
下面是nand Flash和S3C2440A的接口電路:
相應的引腳含義如下：
S3C2440A相應的pin：
ALE：Address latch enable
CLE：Command latch enable
nFCE：Nand flash chip enable
nFRE：Nand flash read enable
nFWE：Nand flash write enable
FRnB：Nand flash ready/busy
NCON：Nand flash configuration（上面已經(jīng)有解釋了）
Nand Flash（非線(xiàn)性存儲器，即不是通過(guò)線(xiàn)性、連續的地址進(jìn)行尋址）不同于Nor Flash（線(xiàn)性存儲器，即通過(guò)連續的地址進(jìn)行尋址），是通過(guò)指令對其進(jìn)行讀、寫(xiě)、塊擦除等各種操作的，而指令又通過(guò)8位I/O端口進(jìn)行傳輸，這樣有效的減少了引腳的數量，也能保證不同容量在引腳、封裝上的兼容，利于系統升級。
分析pin configuration的時(shí)候手冊上有address cycle selection,這里分析它的原因-Nand Flash的尋址方式。Nand Flash存儲容量以page、block為單位，64MB的Nand Flash共有4096個(gè)block，每個(gè)block有32個(gè)page，每個(gè)page包含512 Btyes+16Btye（冗余區，用于存放壞塊標志、塊邏輯地址頁(yè)內數據的ECC checksum等）。具體見(jiàn)下圖（K9f1208U0M）：
可以看出有效數據的存儲單元有512Byte*32page*4096block=64MB，尋址需要9位Column address（512=2^9,即page內的offset），5位page address（32=2^5）和12位block address（4096=2^12）,共26為地址（64MB=2^26）
下圖是K9f1208U0M的address cycle：
因為Nand Flash只能通過(guò)8位I/O port進(jìn)行地址傳送（即，總線(xiàn)的寬度是8位），所以上圖要4個(gè)cycle才能完成尋址。如果是32MB一下的Nand Flash，那么最高使用A24就OK了，這樣只要3個(gè)cycle addressing就能搞定。
NOTE：
上面的疑問(wèn)column address是9位，為什么上面column address卻是A0~A7？仔細看圖會(huì )發(fā)現沒(méi)有A8，這是因為Nand Flash將一個(gè)page的512Byte分成了第一個(gè)half page和第二個(gè)half page，這half page有A0~A8尋址，再通過(guò)命令分別設置A8的值以確定尋址的是那個(gè)half page。
